Copyright © Cullen Programming 1987, 2014
All Rights Reserved
simfifo
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09:26:59 FIFO Simulation 100 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 442
Count of PAGEINS : 558
Count of PAGEOUTS : 135
Count of PAGEOUTS skipped : 423
Time Units spent PAGING : 6930
Avg Cycles a page is resident : 2.85304659 (locality)
Page Hit Ratio : 44.2%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.389 58.088 40.933 25.733 14.766
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09:27:18 FIFO Simulation 200 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 864
Count of PAGEINS : 1136
Count of PAGEOUTS : 334
Count of PAGEOUTS skipped : 802
Time Units spent PAGING : 14700
Avg Cycles a page is resident : 2.81161972 (locality)
Page Hit Ratio : 43.2%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
88.023 59.514 42.363 26.873 15.522
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09:28:02 FIFO Simulation 400 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 1660
Count of PAGEINS : 2340
Count of PAGEOUTS : 597
Count of PAGEOUTS skipped : 1743
Time Units spent PAGING : 29370
Avg Cycles a page is resident : 2.73162393 (locality)
Page Hit Ratio : 41.5%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
88.013 59.489 42.338 26.853 15.509
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09:29:20 FIFO Simulation 800 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 3493
Count of PAGEINS : 4507
Count of PAGEOUTS : 1257
Count of PAGEOUTS skipped : 3250
Time Units spent PAGING : 57640
Avg Cycles a page is resident : 2.83869536 (locality)
Page Hit Ratio : 43.6625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.812 59.033 41.877 26.484 15.263
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09:31:55 FIFO Simulation 1600 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 6893
Count of PAGEINS : 9107
Count of PAGEOUTS : 2484
Count of PAGEOUTS skipped : 6623
Time Units spent PAGING : 115910
Avg Cycles a page is resident : 2.81036565 (locality)
Page Hit Ratio : 43.08125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.870 59.164 42.010 26.590 15.333
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09:35:48 FIFO Simulation 3200 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 13741
Count of PAGEINS : 18259
Count of PAGEOUTS : 5004
Count of PAGEOUTS skipped : 13255
Time Units spent PAGING : 232630
Avg Cycles a page is resident : 2.80354893 (locality)
Page Hit Ratio : 42.940625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.907 59.249 42.095 26.658 15.379
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09:45:21 FIFO Simulation 6400 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 27864
Count of PAGEINS : 36136
Count of PAGEOUTS : 9893
Count of PAGEOUTS skipped : 26243
Time Units spent PAGING : 460290
Avg Cycles a page is resident : 2.83357317 (locality)
Page Hit Ratio : 43.5375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.793 58.989 41.833 26.449 15.239
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09:57:41 FIFO Simulation 12800 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 55318
Count of PAGEINS : 72682
Count of PAGEOUTS : 19843
Count of PAGEOUTS skipped : 52839
Time Units spent PAGING : 925250
Avg Cycles a page is resident : 2.81764398 (locality)
Page Hit Ratio : 43.2171875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.847 59.111 41.956 26.547 15.305
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10:01:54 FIFO Simulation 100 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 692
Count of PAGEINS : 308
Count of PAGEOUTS : 81
Count of PAGEOUTS skipped : 227
Time Units spent PAGING : 3890
Avg Cycles a page is resident : 10.1103896 (locality)
Page Hit Ratio : 69.2%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
79.550 43.757 28.005 16.282 8.8630
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10:01:57 FIFO Simulation 200 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1403
Count of PAGEINS : 597
Count of PAGEOUTS : 138
Count of PAGEOUTS skipped : 459
Time Units spent PAGING : 7350
Avg Cycles a page is resident : 10.5862647 (locality)
Page Hit Ratio : 70.15%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
78.609 42.363 26.873 15.522 8.4144
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10:02:07 FIFO Simulation 400 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 2964
Count of PAGEINS : 1036
Count of PAGEOUTS : 300
Count of PAGEOUTS skipped : 736
Time Units spent PAGING : 13360
Avg Cycles a page is resident : 12.25 (locality)
Page Hit Ratio : 74.1%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
76.958 40.047 25.037 14.310 7.7065
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10:02:27 FIFO Simulation 800 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 5872
Count of PAGEINS : 2128
Count of PAGEOUTS : 573
Count of PAGEOUTS skipped : 1555
Time Units spent PAGING : 27010
Avg Cycles a page is resident : 11.9971805 (locality)
Page Hit Ratio : 73.4%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.149 40.307 25.240 14.443 7.7836
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10:04:32 FIFO Simulation 1600 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 11661
Count of PAGEINS : 4339
Count of PAGEOUTS : 1139
Count of PAGEOUTS skipped : 3200
Time Units spent PAGING : 54780
Avg Cycles a page is resident : 11.7861258 (locality)
Page Hit Ratio : 72.88125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.394 40.644 25.505 14.616 7.8845
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10:09:48 FIFO Simulation 3200 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 23288
Count of PAGEINS : 8712
Count of PAGEOUTS : 2315
Count of PAGEOUTS skipped : 6397
Time Units spent PAGING : 110270
Avg Cycles a page is resident : 11.7479339 (locality)
Page Hit Ratio : 72.775%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.507 40.799 25.628 14.697 7.9315
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10:19:17 FIFO Simulation 6400 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 46288
Count of PAGEINS : 17712
Count of PAGEOUTS : 4837
Count of PAGEOUTS skipped : 12875
Time Units spent PAGING : 225490
Avg Cycles a page is resident : 11.558322 (locality)
Page Hit Ratio : 72.325%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.892 41.337 26.053 14.977 8.0951
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10:42:08 FIFO Simulation 12800 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 93187
Count of PAGEINS : 34813
Count of PAGEOUTS : 9426
Count of PAGEOUTS skipped : 25387
Time Units spent PAGING : 442390
Avg Cycles a page is resident : 11.7637377 (locality)
Page Hit Ratio : 72.8023438%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.559 40.871 25.684 14.734 7.9532
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10:58:47 FIFO Simulation 100 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 843
Count of PAGEINS : 157
Count of PAGEOUTS : 21
Count of PAGEOUTS skipped : 136
Time Units spent PAGING : 1780
Avg Cycles a page is resident : 35.8152866 (locality)
Page Hit Ratio : 84.3%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
64.028 26.253 15.110 8.1726 4.2604
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10:58:49 FIFO Simulation 200 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1752
Count of PAGEINS : 248
Count of PAGEOUTS : 61
Count of PAGEOUTS skipped : 187
Time Units spent PAGING : 3090
Avg Cycles a page is resident : 49.2056452 (locality)
Page Hit Ratio : 87.6%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
60.707 23.605 13.382 7.1710 3.7188
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10:58:56 FIFO Simulation 400 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 3546
Count of PAGEINS : 454
Count of PAGEOUTS : 107
Count of PAGEOUTS skipped : 347
Time Units spent PAGING : 5610
Avg Cycles a page is resident : 54.6101322 (locality)
Page Hit Ratio : 88.65%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
58.376 21.905 12.299 6.5529 3.3874
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10:59:06 FIFO Simulation 800 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 7192
Count of PAGEINS : 808
Count of PAGEOUTS : 187
Count of PAGEOUTS skipped : 621
Time Units spent PAGING : 9950
Avg Cycles a page is resident : 62.5136139 (locality)
Page Hit Ratio : 89.9%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
55.431 19.919 11.061 5.8546 3.0156
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10:59:36 FIFO Simulation 1600 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 14297
Count of PAGEINS : 1703
Count of PAGEOUTS : 461
Count of PAGEOUTS skipped : 1242
Time Units spent PAGING : 21640
Avg Cycles a page is resident : 59.6711685 (locality)
Page Hit Ratio : 89.35625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
57.492 21.290 11.913 6.3341 3.2706
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11:00:28 FIFO Simulation 3200 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 28576
Count of PAGEINS : 3424
Count of PAGEOUTS : 930
Count of PAGEOUTS skipped : 2494
Time Units spent PAGING : 43540
Avg Cycles a page is resident : 59.5794393 (locality)
Page Hit Ratio : 89.3%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
57.638 21.391 11.976 6.3697 3.2896
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11:02:10 FIFO Simulation 6400 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 57576
Count of PAGEINS : 6424
Count of PAGEOUTS : 1703
Count of PAGEOUTS skipped : 4721
Time Units spent PAGING : 81270
Avg Cycles a page is resident : 63.6639166 (locality)
Page Hit Ratio : 89.9625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
55.944 20.253 11.267 5.9701 3.0769
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11:05:26 FIFO Simulation 12800 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 114833
Count of PAGEINS : 13167
Count of PAGEOUTS : 3481
Count of PAGEOUTS skipped : 9686
Time Units spent PAGING : 166480
Avg Cycles a page is resident : 62.1686033 (locality)
Page Hit Ratio : 89.7132813%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
56.533 20.642 11.509 6.1060 3.1491
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11:12:02 FIFO Simulation 100 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 912
Count of PAGEINS : 88
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 88
Time Units spent PAGING : 880
Avg Cycles a page is resident : 71.7386364 (locality)
Page Hit Ratio : 91.2%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
46.808 14.965 8.0882 4.2145 2.1526
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11:12:12 FIFO Simulation 200 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1901
Count of PAGEINS : 99
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 99
Time Units spent PAGING : 990
Avg Cycles a page is resident : 162.919192 (locality)
Page Hit Ratio : 95.05%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
33.110 9.0081 4.7165 2.4152 1.2223
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11:12:17 FIFO Simulation 400 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 3900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 361.31 (locality)
Page Hit Ratio : 97.5%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
200000 4.7619 2.4390 1.2345 0.6211
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11:12:27 FIFO Simulation 800 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 7900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 764.39 (locality)
Page Hit Ratio : 98.75%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
11.111 2.4390 1.2345 0.6211 0.3115
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11:12:46 FIFO Simulation 1600 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 15900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 1566.8 (locality)
Page Hit Ratio : 99.375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
5.8823 1.2345 0.6211 0.3115 0.1560
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11:13:23 FIFO Simulation 3200 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 31900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 3159.38 (locality)
Page Hit Ratio : 99.6875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
3.0303 0.6211 0.3115 0.1560 0.0780
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11:14:39 FIFO Simulation 6400 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 63900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 6351.57 (locality)
Page Hit Ratio : 99.84375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
1.5384 0.3115 0.1560 0.0780 0.0390
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11:17:14 FIFO Simulation 12800 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 127900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 12753.9 (locality)
Page Hit Ratio : 99.921875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
0.7751 0.1560 0.0780 0.0390 0.0195
6911.179643
Ready;
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Copyright © Cullen Programming 1987, 2014 All Rights Reserved |