Copyright © Cullen Programming 1987, 2014
All Rights Reserved
simlru
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09:18:01 LRU Simulation 100 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 501
Count of PAGEINS : 499
Count of PAGEOUTS : 147
Count of PAGEOUTS skipped : 352
Time Units spent PAGING : 6460
Avg Cycles a page is resident : 3.19438878 (locality)
Page Hit Ratio : 50.1%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.595 56.369 39.246 24.414 13.904
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09:18:02 LRU Simulation 200 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 967
Count of PAGEINS : 1033
Count of PAGEOUTS : 296
Count of PAGEOUTS skipped : 737
Time Units spent PAGING : 13290
Avg Cycles a page is resident : 3.0909971 (locality)
Page Hit Ratio : 48.35%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.919 57.063 39.921 24.939 14.245
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09:18:06 LRU Simulation 400 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 1967
Count of PAGEINS : 2033
Count of PAGEOUTS : 545
Count of PAGEOUTS skipped : 1488
Time Units spent PAGING : 25780
Avg Cycles a page is resident : 3.14510576 (locality)
Page Hit Ratio : 49.175%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.568 56.312 39.191 24.371 13.876
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09:18:18 LRU Simulation 800 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 4016
Count of PAGEINS : 3984
Count of PAGEOUTS : 1059
Count of PAGEOUTS skipped : 2925
Time Units spent PAGING : 50430
Avg Cycles a page is resident : 3.21134538 (locality)
Page Hit Ratio : 50.2%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.308 55.766 38.664 23.965 13.613
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09:18:31 LRU Simulation 1600 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 7954
Count of PAGEINS : 8046
Count of PAGEOUTS : 2131
Count of PAGEOUTS skipped : 5915
Time Units spent PAGING : 101770
Avg Cycles a page is resident : 3.18095948 (locality)
Page Hit Ratio : 49.7125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.414 55.988 38.877 24.129 13.719
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09:18:57 LRU Simulation 3200 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 15889
Count of PAGEINS : 16111
Count of PAGEOUTS : 4372
Count of PAGEOUTS skipped : 11739
Time Units spent PAGING : 204830
Avg Cycles a page is resident : 3.17751847 (locality)
Page Hit Ratio : 49.653125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.488 56.143 39.027 24.245 13.794
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09:19:49 LRU Simulation 6400 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 31844
Count of PAGEINS : 32156
Count of PAGEOUTS : 8689
Count of PAGEOUTS skipped : 23467
Time Units spent PAGING : 408450
Avg Cycles a page is resident : 3.1841958 (locality)
Page Hit Ratio : 49.75625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.453 56.071 38.957 24.190 13.759
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09:21:33 LRU Simulation 12800 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 63705
Count of PAGEINS : 64295
Count of PAGEOUTS : 17370
Count of PAGEOUTS skipped : 46925
Time Units spent PAGING : 816650
Avg Cycles a page is resident : 3.18522436 (locality)
Page Hit Ratio : 49.7695313%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
86.450 56.063 38.950 24.185 13.756
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09:25:07 LRU Simulation 100 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 797
Count of PAGEINS : 203
Count of PAGEOUTS : 58
Count of PAGEOUTS skipped : 145
Time Units spent PAGING : 2610
Avg Cycles a page is resident : 15.3694581 (locality)
Page Hit Ratio : 79.7%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
72.299 34.296 20.697 11.543 6.1253
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09:25:09 LRU Simulation 200 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1637
Count of PAGEINS : 363
Count of PAGEOUTS : 88
Count of PAGEOUTS skipped : 275
Time Units spent PAGING : 4510
Avg Cycles a page is resident : 17.4545455 (locality)
Page Hit Ratio : 81.85%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
69.278 31.082 18.400 10.132 5.3366
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09:25:13 LRU Simulation 400 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 3322
Count of PAGEINS : 678
Count of PAGEOUTS : 179
Count of PAGEOUTS skipped : 499
Time Units spent PAGING : 8570
Avg Cycles a page is resident : 18.7846608 (locality)
Page Hit Ratio : 83.05%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
68.178 29.996 17.644 9.6759 5.0839
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09:25:20 LRU Simulation 800 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 6700
Count of PAGEINS : 1300
Count of PAGEOUTS : 345
Count of PAGEOUTS skipped : 955
Time Units spent PAGING : 16450
Avg Cycles a page is resident : 19.6069231 (locality)
Page Hit Ratio : 83.75%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
67.280 29.140 17.055 9.3227 4.8892
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09:25:36 LRU Simulation 1600 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 13553
Count of PAGEINS : 2447
Count of PAGEOUTS : 685
Count of PAGEOUTS skipped : 1762
Time Units spent PAGING : 31320
Avg Cycles a page is resident : 20.8888435 (locality)
Page Hit Ratio : 84.70625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
66.187 28.135 16.370 8.9149 4.6654
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09:26:07 LRU Simulation 3200 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 26683
Count of PAGEINS : 5317
Count of PAGEOUTS : 1456
Count of PAGEOUTS skipped : 3861
Time Units spent PAGING : 67730
Avg Cycles a page is resident : 19.2456272 (locality)
Page Hit Ratio : 83.384375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
67.913 29.741 17.468 9.5700 5.0254
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09:27:20 LRU Simulation 6400 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 53633
Count of PAGEINS : 10367
Count of PAGEOUTS : 2781
Count of PAGEOUTS skipped : 7586
Time Units spent PAGING : 131480
Avg Cycles a page is resident : 19.7487219 (locality)
Page Hit Ratio : 83.8015625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
67.260 29.121 17.042 9.3150 4.8850
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09:29:40 LRU Simulation 12800 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 107292
Count of PAGEINS : 20708
Count of PAGEOUTS : 5585
Count of PAGEOUTS skipped : 15123
Time Units spent PAGING : 262930
Avg Cycles a page is resident : 19.7763666 (locality)
Page Hit Ratio : 83.821875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
67.257 29.119 17.040 9.3140 4.8845
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09:34:28 LRU Simulation 100 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 887
Count of PAGEINS : 113
Count of PAGEOUTS : 8
Count of PAGEOUTS skipped : 105
Time Units spent PAGING : 1210
Avg Cycles a page is resident : 47.5929204 (locality)
Page Hit Ratio : 88.7%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
54.751 19.484 10.793 5.7048 2.9361
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09:34:31 LRU Simulation 200 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1817
Count of PAGEINS : 183
Count of PAGEOUTS : 36
Count of PAGEOUTS skipped : 147
Time Units spent PAGING : 2190
Avg Cycles a page is resident : 66.3333333 (locality)
Page Hit Ratio : 90.85%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
52.267 17.965 9.8693 5.1908 2.6645
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09:34:36 LRU Simulation 400 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 3678
Count of PAGEINS : 322
Count of PAGEOUTS : 73
Count of PAGEOUTS skipped : 249
Time Units spent PAGING : 3950
Avg Cycles a page is resident : 77.3695652 (locality)
Page Hit Ratio : 91.95%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
49.685 16.492 8.9874 4.7051 2.4092
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09:34:46 LRU Simulation 800 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 7319
Count of PAGEINS : 681
Count of PAGEOUTS : 183
Count of PAGEOUTS skipped : 498
Time Units spent PAGING : 8640
Avg Cycles a page is resident : 74.1380323 (locality)
Page Hit Ratio : 91.4875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
51.923 17.763 9.7472 5.1233 2.6290
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09:35:06 LRU Simulation 1600 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 14789
Count of PAGEINS : 1211
Count of PAGEOUTS : 296
Count of PAGEOUTS skipped : 915
Time Units spent PAGING : 15070
Avg Cycles a page is resident : 83.8918249 (locality)
Page Hit Ratio : 92.43125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
48.503 15.851 8.6079 4.4975 2.3005
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09:35:52 LRU Simulation 3200 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 29613
Count of PAGEINS : 2387
Count of PAGEOUTS : 603
Count of PAGEOUTS skipped : 1784
Time Units spent PAGING : 29900
Avg Cycles a page is resident : 85.4763301 (locality)
Page Hit Ratio : 92.540625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
48.303 15.745 8.5452 4.4633 2.2826
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09:37:13 LRU Simulation 6400 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 59352
Count of PAGEINS : 4648
Count of PAGEOUTS : 1228
Count of PAGEOUTS skipped : 3420
Time Units spent PAGING : 58760
Avg Cycles a page is resident : 87.9492255 (locality)
Page Hit Ratio : 92.7375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
47.865 15.513 8.4091 4.3891 2.2438
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09:40:00 LRU Simulation 12800 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 118557
Count of PAGEINS : 9443
Count of PAGEOUTS : 2496
Count of PAGEOUTS skipped : 6947
Time Units spent PAGING : 119390
Avg Cycles a page is resident : 86.6867521 (locality)
Page Hit Ratio : 92.6226563%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
48.259 15.721 8.5315 4.4558 2.2787
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09:45:36 LRU Simulation 100 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 909
Count of PAGEINS : 91
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 91
Time Units spent PAGING : 910
Avg Cycles a page is resident : 75.1208791 (locality)
Page Hit Ratio : 90.9%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
47.643 15.397 8.3409 4.3519 2.2243
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09:45:39 LRU Simulation 200 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 153.23 (locality)
Page Hit Ratio : 95%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
33.333 9.0909 4.7619 2.4390 1.2345
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09:45:51 LRU Simulation 400 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 3900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 359.05 (locality)
Page Hit Ratio : 97.5%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
200000 4.7619 2.4390 1.2345 0.6211
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09:46:02 LRU Simulation 800 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 7900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 758.91 (locality)
Page Hit Ratio : 98.75%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
11.111 2.4390 1.2345 0.6211 0.3115
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09:46:24 LRU Simulation 1600 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 15900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 1550.69 (locality)
Page Hit Ratio : 99.375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
5.8823 1.2345 0.6211 0.3115 0.1560
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09:47:06 LRU Simulation 3200 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 31900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 3157.25 (locality)
Page Hit Ratio : 99.6875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
3.0303 0.6211 0.3115 0.1560 0.0780
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09:48:28 LRU Simulation 6400 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 63900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 6357.39 (locality)
Page Hit Ratio : 99.84375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
1.5384 0.3115 0.1560 0.0780 0.0390
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09:51:23 LRU Simulation 12800 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 127900
Count of PAGEINS : 100
Count of PAGEOUTS : 0
Count of PAGEOUTS skipped : 100
Time Units spent PAGING : 1000
Avg Cycles a page is resident : 12759.82 (locality)
Page Hit Ratio : 99.921875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
0.7751 0.1560 0.0780 0.0390 0.0195
2340.184244
Ready;
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Copyright © Cullen Programming 1987, 2014 All Rights Reserved |