Copyright © Cullen Programming 1987, 2014
All Rights Reserved
simrand
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10:02:15 RAND Simulation 100 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 443
Count of PAGEINS : 557
Count of PAGEOUTS : 133
Count of PAGEOUTS skipped : 424
Time Units spent PAGING : 6900
Avg Cycles a page is resident : 2.81687612 (locality)
Page Hit Ratio : 44.3%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.341 57.983 40.828 25.650 14.712
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10:02:17 RAND Simulation 200 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 896
Count of PAGEINS : 1104
Count of PAGEOUTS : 312
Count of PAGEOUTS skipped : 792
Time Units spent PAGING : 14160
Avg Cycles a page is resident : 2.86775362 (locality)
Page Hit Ratio : 44.8%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.623 58.609 41.451 26.144 15.038
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10:02:20 RAND Simulation 400 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 1731
Count of PAGEINS : 2269
Count of PAGEOUTS : 619
Count of PAGEOUTS skipped : 1650
Time Units spent PAGING : 28880
Avg Cycles a page is resident : 2.80564125 (locality)
Page Hit Ratio : 43.275%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.834 59.083 41.927 26.524 15.290
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10:02:33 RAND Simulation 800 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 3527
Count of PAGEINS : 4473
Count of PAGEOUTS : 1199
Count of PAGEOUTS skipped : 3274
Time Units spent PAGING : 56720
Avg Cycles a page is resident : 2.85513078 (locality)
Page Hit Ratio : 44.0875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.639 58.643 41.486 26.172 15.056
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10:02:47 RAND Simulation 1600 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 7138
Count of PAGEINS : 8862
Count of PAGEOUTS : 2405
Count of PAGEOUTS skipped : 6457
Time Units spent PAGING : 112670
Avg Cycles a page is resident : 2.88670729 (locality)
Page Hit Ratio : 44.6125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.565 58.478 41.321 26.040 14.969
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10:03:15 RAND Simulation 3200 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 14231
Count of PAGEINS : 17769
Count of PAGEOUTS : 4901
Count of PAGEOUTS skipped : 12868
Time Units spent PAGING : 226700
Avg Cycles a page is resident : 2.88012831 (locality)
Page Hit Ratio : 44.471875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.630 58.624 41.466 26.156 15.046
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10:04:09 RAND Simulation 6400 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 28426
Count of PAGEINS : 35574
Count of PAGEOUTS : 9656
Count of PAGEOUTS skipped : 25918
Time Units spent PAGING : 452300
Avg Cycles a page is resident : 2.87783212 (locality)
Page Hit Ratio : 44.415625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.604 58.565 41.408 26.109 15.015
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10:05:58 RAND Simulation 12800 Dispatch Cycles for DPA Size of 16 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 56927
Count of PAGEINS : 71073
Count of PAGEOUTS : 19265
Count of PAGEOUTS skipped : 51808
Time Units spent PAGING : 903380
Avg Cycles a page is resident : 2.88123479 (locality)
Page Hit Ratio : 44.4742188%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
87.589 58.532 41.375 26.083 14.997
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10:09:44 RAND Simulation 100 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 720
Count of PAGEINS : 280
Count of PAGEOUTS : 54
Count of PAGEOUTS skipped : 226
Time Units spent PAGING : 3340
Avg Cycles a page is resident : 10.8392857 (locality)
Page Hit Ratio : 72%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
76.958 40.047 25.037 14.310 7.7065
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10:09:46 RAND Simulation 200 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1434
Count of PAGEINS : 566
Count of PAGEOUTS : 151
Count of PAGEOUTS skipped : 415
Time Units spent PAGING : 7170
Avg Cycles a page is resident : 10.8833922 (locality)
Page Hit Ratio : 71.7%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
78.189 41.758 26.389 15.200 8.2253
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10:09:50 RAND Simulation 400 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 2915
Count of PAGEINS : 1085
Count of PAGEOUTS : 301
Count of PAGEOUTS skipped : 784
Time Units spent PAGING : 13860
Avg Cycles a page is resident : 11.6202765 (locality)
Page Hit Ratio : 72.875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.603 40.933 25.733 14.766 7.9719
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10:09:59 RAND Simulation 800 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 5698
Count of PAGEINS : 2302
Count of PAGEOUTS : 589
Count of PAGEOUTS skipped : 1713
Time Units spent PAGING : 28910
Avg Cycles a page is resident : 11.0256299 (locality)
Page Hit Ratio : 71.225%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
78.325 41.953 26.544 15.303 8.2858
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10:10:16 RAND Simulation 1600 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 11627
Count of PAGEINS : 4373
Count of PAGEOUTS : 1198
Count of PAGEOUTS skipped : 3175
Time Units spent PAGING : 55710
Avg Cycles a page is resident : 11.6720787 (locality)
Page Hit Ratio : 72.66875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.687 41.050 25.826 14.827 8.0076
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10:10:50 RAND Simulation 3200 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 23350
Count of PAGEINS : 8650
Count of PAGEOUTS : 2259
Count of PAGEOUTS skipped : 6391
Time Units spent PAGING : 109090
Avg Cycles a page is resident : 11.816185 (locality)
Page Hit Ratio : 72.96875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.319 40.540 25.423 14.563 7.8533
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10:12:04 RAND Simulation 6400 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 46580
Count of PAGEINS : 17420
Count of PAGEOUTS : 4743
Count of PAGEOUTS skipped : 12677
Time Units spent PAGING : 221630
Avg Cycles a page is resident : 11.7486223 (locality)
Page Hit Ratio : 72.78125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.593 40.919 25.722 14.759 7.9676
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10:14:20 RAND Simulation 12800 Dispatch Cycles for DPA Size of 32 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 92919
Count of PAGEINS : 35081
Count of PAGEOUTS : 9681
Count of PAGEOUTS skipped : 25400
Time Units spent PAGING : 447620
Avg Cycles a page is resident : 11.6703629 (locality)
Page Hit Ratio : 72.5929688%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
77.763 41.155 25.909 14.882 8.0397
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10:19:02 RAND Simulation 100 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 840
Count of PAGEINS : 160
Count of PAGEOUTS : 23
Count of PAGEOUTS skipped : 137
Time Units spent PAGING : 1830
Avg Cycles a page is resident : 30.4625 (locality)
Page Hit Ratio : 84%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
64.664 26.793 15.469 8.3829 4.3748
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10:19:05 RAND Simulation 200 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1701
Count of PAGEINS : 299
Count of PAGEOUTS : 64
Count of PAGEOUTS skipped : 235
Time Units spent PAGING : 3630
Avg Cycles a page is resident : 36.7458194 (locality)
Page Hit Ratio : 85.05%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
64.476 26.632 15.361 8.3199 4.3405
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10:19:12 RAND Simulation 400 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 3509
Count of PAGEINS : 491
Count of PAGEOUTS : 115
Count of PAGEOUTS skipped : 376
Time Units spent PAGING : 6060
Avg Cycles a page is resident : 47.8940937 (locality)
Page Hit Ratio : 87.725%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
60.238 23.254 13.156 7.0415 3.6492
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10:19:30 RAND Simulation 800 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 7105
Count of PAGEINS : 895
Count of PAGEOUTS : 229
Count of PAGEOUTS skipped : 666
Time Units spent PAGING : 11240
Avg Cycles a page is resident : 55.2905028 (locality)
Page Hit Ratio : 88.8125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
58.419 21.935 12.319 6.5638 3.3933
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10:19:55 RAND Simulation 1600 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 14305
Count of PAGEINS : 1695
Count of PAGEOUTS : 431
Count of PAGEOUTS skipped : 1264
Time Units spent PAGING : 21260
Avg Cycles a page is resident : 59.1929204 (locality)
Page Hit Ratio : 89.40625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
57.058 20.995 11.729 6.2298 3.2150
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10:20:52 RAND Simulation 3200 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 28612
Count of PAGEINS : 3388
Count of PAGEOUTS : 923
Count of PAGEOUTS skipped : 2465
Time Units spent PAGING : 43110
Avg Cycles a page is resident : 59.8952184 (locality)
Page Hit Ratio : 89.4125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
57.395 21.224 11.872 6.3108 3.2582
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10:22:34 RAND Simulation 6400 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 57276
Count of PAGEINS : 6724
Count of PAGEOUTS : 1819
Count of PAGEOUTS skipped : 4905
Time Units spent PAGING : 85430
Avg Cycles a page is resident : 60.7018144 (locality)
Page Hit Ratio : 89.49375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
57.170 21.071 11.776 6.2566 3.2293
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10:25:54 RAND Simulation 12800 Dispatch Cycles for DPA Size of 64 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 114832
Count of PAGEINS : 13168
Count of PAGEOUTS : 3625
Count of PAGEOUTS skipped : 9543
Time Units spent PAGING : 167930
Avg Cycles a page is resident : 62.0789793 (locality)
Page Hit Ratio : 89.7125%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
56.746 20.785 11.597 6.1559 3.1757
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10:32:37 RAND Simulation 100 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 1000
Count of PAGES found resident : 896
Count of PAGEINS : 104
Count of PAGEOUTS : 11
Count of PAGEOUTS skipped : 93
Time Units spent PAGING : 1150
Avg Cycles a page is resident : 59.2980769 (locality)
Page Hit Ratio : 89.6%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
53.488 18.699 10.313 5.4373 2.7946
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10:32:42 RAND Simulation 200 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 2000
Count of PAGES found resident : 1847
Count of PAGEINS : 153
Count of PAGEOUTS : 17
Count of PAGEOUTS skipped : 136
Time Units spent PAGING : 1700
Avg Cycles a page is resident : 94.5751634 (locality)
Page Hit Ratio : 92.35%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
45.945 14.529 7.8341 4.0767 2.0807
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10:32:58 RAND Simulation 400 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 4000
Count of PAGES found resident : 3806
Count of PAGEINS : 194
Count of PAGEOUTS : 21
Count of PAGEOUTS skipped : 173
Time Units spent PAGING : 2150
Avg Cycles a page is resident : 167.386598 (locality)
Page Hit Ratio : 95.15%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
34.959 9.7065 5.1008 2.6171 1.3259
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10:33:17 RAND Simulation 800 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 8000
Count of PAGES found resident : 7827
Count of PAGEINS : 173
Count of PAGEOUTS : 19
Count of PAGEOUTS skipped : 154
Time Units spent PAGING : 1920
Avg Cycles a page is resident : 423.115607 (locality)
Page Hit Ratio : 97.8375%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
19.354 4.5801 2.3437 1.1857 0.5964
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10:34:00 RAND Simulation 1600 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 16000
Count of PAGES found resident : 15787
Count of PAGEINS : 213
Count of PAGEOUTS : 34
Count of PAGEOUTS skipped : 179
Time Units spent PAGING : 2470
Avg Cycles a page is resident : 712.413146 (locality)
Page Hit Ratio : 98.66875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
13.373 2.9950 1.5202 0.7659 0.3844
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10:35:26 RAND Simulation 3200 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 32000
Count of PAGES found resident : 31815
Count of PAGEINS : 185
Count of PAGEOUTS : 23
Count of PAGEOUTS skipped : 162
Time Units spent PAGING : 2080
Avg Cycles a page is resident : 1687.85946 (locality)
Page Hit Ratio : 99.421875%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
6.1032 1.2833 0.6458 0.3239 0.1622
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10:38:01 RAND Simulation 6400 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 64000
Count of PAGES found resident : 63834
Count of PAGEINS : 166
Count of PAGEOUTS : 17
Count of PAGEOUTS skipped : 149
Time Units spent PAGING : 1830
Avg Cycles a page is resident : 3817.92169 (locality)
Page Hit Ratio : 99.740625%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
2.7798 0.5686 0.2851 0.1427 0.0714
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10:44:09 RAND Simulation 12800 Dispatch Cycles for DPA Size of 128 frames
Count of PAGE ACCESSES : 128000
Count of PAGES found resident : 127815
Count of PAGEINS : 185
Count of PAGEOUTS : 20
Count of PAGEOUTS skipped : 165
Time Units spent PAGING : 2050
Avg Cycles a page is resident : 6883.61622 (locality)
Page Hit Ratio : 99.8554688%
Percentage of Wall Clock time performing paging operations
T1=1msec T2=5msec T3=10msec T4=20msec T5=40msec (CPU tslice)
1.5763 0.3192 0.1599 0.0800 0.0400
3185.853327
Ready;
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Copyright © Cullen Programming 1987, 2014 All Rights Reserved |